Global Leading Market Research Publisher QYResearch announces the release of its latest report “In-memory Computing Chips – Global Market Share and Ranking, Overall Sales and Demand Forecast 2026-2032”. Based on current situation and impact historical analysis (2021-2025) and forecast calculations (2026-2032), this report provides a comprehensive analysis of the global In-memory Computing Chips market, including market size, share, demand, industry development status, and forecasts for the next few years.
The global market for In-memory Computing Chips was estimated to be worth US231millionin2025andisprojectedtoreachUS231millionin2025andisprojectedtoreachUS 44,335 million, growing at a CAGR of 112.4% from 2026 to 2032.
In-Memory Computing Chips are computing devices that perform calculations directly within memory arrays or in very close proximity to them, rather than moving data back and forth between separate memory and processing units. By integrating computation into memory, these chips significantly reduce data movement, which lowers power consumption, decreases latency, and alleviates memory bandwidth limitations inherent in traditional von Neumann architectures. In-memory computing chips are particularly well suited for AI and machine-learning workloads dominated by matrix and vector operations, and are typically implemented using SRAM, DRAM, or emerging non-volatile memory technologies, making them a promising solution for energy-efficient edge AI and next-generation computing systems.
Hardware architects, AI system designers, and edge computing engineers face a fundamental and escalating challenge: the von Neumann bottleneck, where shuttling data between processor and memory consumes 80-90% of energy and dominates execution time for AI workloads. For large language model inference (70B-parameter class), data movement accounts for 85% of energy and 70% of latency. For edge devices (smart sensors, wearables, robotics), conventional MCUs and NPUs exceed power budgets for always-on AI, limiting battery life and deployment scenarios. In-memory computing chips address this bottleneck by integrating compute capabilities directly into memory arrays (SRAM, DRAM, ReRAM), performing matrix-vector multiplication (core of neural networks) where data resides. This approach achieves 10-100x improvement in energy efficiency (10-300 TOPS/W vs. 1-10 TOPS/W for conventional accelerators) and 5-20x reduction in latency for memory-bound operations. This report delivers data-driven insights into market size, architecture-type segmentation (PIM vs. CIM), computing power classification, and technology maturation across the 2026-2032 forecast period.
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1. Core Keywords and Market Definition: Processing-in-Memory (PIM), Compute-in-Memory (CIM), and Multiply-Accumulate (MAC) Throughput
This analysis embeds three core keywords—Processing-in-Memory (PIM) , Compute-in-Memory (CIM) , and Multiply-Accumulate (MAC) Throughput—throughout the industry narrative. These terms define the architectural spectrum and key performance metrics for in-memory computing chips.
Processing-in-Memory (PIM) integrates compute logic on the same die or package as memory, with processing units located near memory arrays (e.g., at sense amplifiers or within DRAM banks). Data moves within the memory chip but avoids long-distance transfer to a separate host processor. PIM retains digital precision (8-16 bit) and programmability, making it suitable for data center inference and training acceleration. Examples: Samsung HBM-PIM (processing-in-memory integrated with HBM3), SK Hynix AiM (acceleration-in-memory), UPMEM DDR4 DIMMs. PIM offers 3-10x efficiency gain vs. conventional architectures. PIM accounted for 45% of in-memory computing chip revenue in 2025.
Compute-in-Memory (CIM) goes further: compute (MAC operations) occurs inside memory arrays using analog or digital circuits that share bitlines and wordlines. Analog CIM uses charge sharing or current summing (highest efficiency, 50-300 TOPS/W, but limited to 4-8 bit precision). Digital CIM places small MAC units at each column (8-16 bits, 10-30 TOPS/W). CIM requires custom memory array design (cannot retrofit standard DRAM/SRAM). Examples: Myhtic (analog CIM), Syntiant (SRAM-CIM), EnCharge AI (analog CIM). CIM efficiency 10-100x vs. conventional. CIM accounted for 55% of revenue in 2025.
Multiply-Accumulate (MAC) Throughput measured in TOPS (tera-operations per second) and TOPS/W (efficiency). For AI workloads (matrix multiplication), MAC throughput directly correlates with inference speed. Comparative (2025-2026): NVIDIA H100 GPU: 1,979 TOPS INT8, efficiency 2.4 TOPS/W. Samsung HBM-PIM: 1,600 TOPS per stack, efficiency 6-8 TOPS/W. Digital SRAM-CIM (Syntiant): 10-30 TOPS/W. Analog CIM (Myhtic): 50-300 TOPS/W but limited precision.
2. Industry Depth: PIM vs. CIM Architecture Comparison
| Architecture | Compute Location | Memory Type | Precision | TOPS/W (estimated) | Programmability | Maturity | Primary Applications | Market Share (2025 revenue) | CAGR (2026-2032) |
|---|---|---|---|---|---|---|---|---|---|
| PIM (Processing-in-Memory) | Near memory arrays (sense amps, bank logic) | DRAM (HBM, DDR), SRAM | 8-16 bit | 5-10 | Moderate (limited opcodes) | Production (Samsung, SK Hynix 2021+) | Data center inference, LLM, recommendation systems | 45% | 110% |
| CIM (Compute-in-Memory) – Digital | Inside memory array (shared bitlines) | SRAM (primary) | 8-16 bit | 10-30 | High (custom compute) | Mature (edge products 2019+) | Edge inference (voice, vision, sensor fusion) | 40% | 115% |
| CIM – Analog | Inside memory array (charge/current domain) | SRAM, ReRAM, MRAM | 4-8 bit | 50-300 | Low (fixed functions) | Commercial pilot (2024-2026) | Low-precision edge, medical imaging, defense | 15% | 120% |
Recent 6-Month Industry Data (December 2025 – May 2026):
- Samsung PIM expansion: Samsung announced (March 2026) second-generation HBM-PIM (HBM3e based, 1.2 TB/s bandwidth, 2,400 TOPS per stack). First customer: AMD (MI400 accelerator for inference). Meta (LLaMA-3 optimization) testing PIM for recommendation systems (40% inference cost reduction). Samsung targeting 30% of HBM shipments with PIM by 2028.
- SK Hynix AiM: SK Hynix reported (January 2026) production of AiM GDDR6-AiM (1,600 TOPS, 6-8 TOPS/W) for automotive ADAS inference (preprocessing camera/radar data before GPU). Customer: Hyundai Mobis (2027 model year). Volume: 500,000 units 2026-2027.
- Analog CIM commercial traction: Myhtic (US) announced Q1 2026 revenue 12M(GEHealthcareCTpreprocessing,Siemensindustrialsensors).EnChargeAIsecured12M(GEHealthcareCTpreprocessing,Siemensindustrialsensors).EnChargeAIsecured45M Series B (February 2026) for defense (DARPA) and aerospace (Raytheon) applications. Chinese analog CIM (AistarTek, Beijing Pingxin) focused on smart sensors (Xiaomi, DJI).
- China domestic market: Chinese government “Chip Sovereignty” program allocated 380M(2025−2027)forCIM/PIMdevelopment.HangzhouZhicun(Witmem)SRAM−CIMshipped35Munits2025(mainlyXiaomiwearables).ShenzhenReexentargetingautomotive(BYD).ChinaCIM/PIMmarket2025380M(2025−2027)forCIM/PIMdevelopment.HangzhouZhicun(Witmem)SRAM−CIMshipped35Munits2025(mainlyXiaomiwearables).ShenzhenReexentargetingautomotive(BYD).ChinaCIM/PIMmarket202585M (37% global), projected $14B (32% share) by 2032.
3. Key User Case: Wearable OEM – Digital SRAM-CIM for Always-On Voice Wake Word
A wearable device OEM (smartwatch + earbud manufacturer, 80M units annually) used conventional DSP for always-on voice wake word (60μW active power). Battery life impact: 8% reduction (from 5 days to 4.6 days). User complaints: “my watch needs charging too often.”
OEM evaluated Syntiant SRAM-CIM (NDP120, 8 TOPS/W, 30μW) and Myhtic analog CIM (M1076, 150 TOPS/W, 100μW). Syntiant selected due to production availability (50M units shipped), ecosystem (TensorFlow Lite Micro support), and lower active power (30μW vs. 100μW for Myhtic — analog CIM more efficient at higher utilization, but voice wake word is sparse activity).
Results (deployed in flagship smartwatch, Q1 2026):
- Active power: 28μW (vs. 60μW DSP) → 53% reduction.
- Wake word accuracy: 98% (vs. 97% DSP) — equivalent.
- Battery life improvement: 5 days → 5.6 days (+12%).
- Silicon area: Syntiant NDP120 2.1mm² (28nm) vs. DSP 3.5mm² (40nm).
- Cost: 0.85perchip(DSP0.85perchip(DSP1.20). 80M units → $28M annual savings.
- Integration effort: 3 engineer-months to port wake word model (custom memory mapping, toolchain). DSP migration would have required 6-9 months.
OEM expanding Syntiant CIM to all 2027 models. This case validates the report’s finding that digital SRAM-CIM offers compelling power/cost advantages for always-on edge AI (voice, sensor) with acceptable integration effort.
4. Technology Landscape and Competitive Analysis
The In-memory Computing Chips market is segmented as below:
Major Manufacturers:
DRAM-PIM (Data Center):
- Samsung: Estimated 20% market share (of total in-memory computing revenue). HBM-PIM leader. Key customers: AMD, Meta, Graphcore.
- SK Hynix: Estimated 10% share. AiM (GDDR6, HBM3). Key customers: Hyundai Mobis, Microsoft (Azure).
SRAM-CIM (Edge):
- Syntiant: Estimated 15% share. Cumulative shipments 50M+ units. Key customers: Apple, Google, Amazon, Samsung, Xiaomi.
- Hangzhou Zhicun (Witmem) : Estimated 10% share. Chinese edge CIM leader. Customers: Xiaomi, Oppo, BBK, Baidu.
- Graphcore (UK): Estimated 5% share. IPU uses SRAM-near-memory (PIM-like). Cloud and enterprise.
Analog CIM:
- Myhtic (US): Estimated 8% share. Medical, industrial, defense. Customer: GE Healthcare.
- EnCharge AI (US): Estimated 4% share. Defense, aerospace (DARPA). Customer: Raytheon.
- AistarTek (China): Estimated 3% share. Chinese analog CIM for sensors.
- Beijing Pingxin Technology: Estimated 2% share.
Others (Digital PIM/CIM hybrid, ReRAM, etc.):
- D-Matrix (US): Estimated 3% share. Digital in-memory compute for transformers.
- Axelera AI (Netherlands): Estimated 3% share. Digital CIM for vision (retail, security).
- Beijing Houmo Technology: Estimated 2% share. ReRAM-based CIM (non-volatile).
- Suzhou Yizhu Intelligent Technology: Estimated 2% share.
- Shenzhen Reexen Technology: Estimated 2% share.
Segment by Architecture Type:
- PIM (Processing-in-Memory) : 45% of 2025 revenue. Data center, large models. CAGR 110%.
- CIM (Compute-in-Memory) : 55% of revenue (digital 40%, analog 15%). Edge, embedded. CAGR 115%.
Segment by Computing Power:
- Small Computing Power (sub-1 TOPS, sub-100mW): 35% of 2025 revenue. Edge sensors, wearables, hearables, smart home. CAGR 108%.
- Large Computing Power (>1 TOPS, 0.1W to hundreds of watts): 65% of revenue. Data center inference, automotive ADAS, robotics, smart cameras. CAGR 114%.
Technical Challenges Emerging in 2026:
- Analog CIM precision calibration: Manufacturing variation (10-20% in resistance/capacitance) causes compute errors. Calibration per chip (trimming, look-up tables) adds 0.15−0.40perchip(vs.0.15−0.40perchip(vs.0.01 for digital). Without calibration, analog CIM yields 50-60% at 8-bit precision; with calibration yields 80-85% (still below 95%+ for digital). Myhtic and EnCharge implementing on-chip digital assist (adaptive biasing) — adds 15% area overhead but improves yield to 88-92%.
- Software ecosystem fragmentation: No industry-standard programming model for CIM/PIM. Each vendor requires custom compiler, runtime, operator library. Syntiant (TensorFlow Lite Micro), Samsung (PyTorch plugin), D-Matrix (custom SDK). Industry consortium (PIM Alliance, formed 2024) includes Samsung, SK Hynix, Graphcore, Axelera, AMD — working on open ISA, but ratification not expected before 2028.
- Memory retention vs. compute activity: DRAM-PIM integrates compute within 2-3μm of DRAM cells. Compute activity raises local temperature 10-15°C, accelerating charge leakage. DRAM refresh rate must increase (power penalty) or data retention degrades. Samsung HBM-PIM uses thermal-aware scheduling (compute bursts limited to 10-20μs, cooldown 5-10μs) — reduces performance 5-8% but maintains retention.
- Non-volatile CIM (ReRAM) endurance: ReRAM (Beijing Houmo) offers non-volatile memory + compute (zero standby power). Write endurance limited (10⁵-10⁶ cycles vs. 10¹⁵ for DRAM) — unsuitable for training (frequent weight updates) but acceptable for inference with static weights. ReRAM CIM market <1% of revenue 2025, projected 5-8% by 2032 (defense, aerospace, space).
5. Exclusive Observation: The “Edge-Dominated” vs. “Data Center-PIM” Market Split
Our exclusive analysis identifies a fundamental market split: edge AI dominated by CIM (digital and analog); data center inference dominated by PIM (DRAM-based).
Edge AI (CIM, 65% of 2025 revenue, 55% of projected 2032 revenue) : Requirements: sub-watt power, small form factor, moderate compute (0.1-100 TOPS), low latency. CIM ideal: SRAM-CIM (Syntiant, Witmem) for voice/sensors; analog CIM (Myhtic, EnCharge) for vision/healthcare. Edge CIM market CAGR 115%, reaching $24B by 2032.
Data Center Inference (PIM, 35% of 2025 revenue, 45% of projected 2032 revenue) : Requirements: high throughput (100-10,000 TOPS), integration with existing GPU/CPU infrastructure. PIM (HBM-PIM, AiM) as accelerator co-located with GPU/CPU. Data center PIM market CAGR 110%, reaching $20B by 2032.
Notable crossover: Chinese domestic market — data center CIM (digital) emerging (Beijing Houmo ReRAM, Suzhou Yizhu) due to GPU export restrictions (US ban on NVIDIA H100 to China). Chinese data centers have no choice but to adopt alternative accelerators (CIM, ASIC, FPGA). China data center CIM market 2025 45M,projected45M,projected3B by 2030.
Second-tier insight: The automotive ADAS segment (camera/radar preprocessing before main GPU) is adopting PIM/CIM to reduce data bandwidth to GPU. Example: 8 cameras @ 30fps, 1080p = 8Gbps raw data. GPU cannot process all; must downsample or drop frames. SK Hynix AiM (GDDR6-PIM) preprocesses (frame differencing, object detection, cropping) before sending to GPU, reducing bandwidth 70%. Hyundai Mobis deploying AiM in 2027 premium EV (3,000 TOPS, 15W). Automotive CIM/PIM market 2025 30M,projected30M,projected5B by 2032 (11% of total).
6. Forecast Implications (2026–2032)
The report projects in-memory computing chips market to grow at 112.4% CAGR through 2032, reaching $44.3 billion — the fastest-growing segment in computing hardware. CIM architecture will slightly outpace PIM (CAGR 115% vs. 110%) due to edge AI proliferation. Edge/small computing power will capture 55% of revenue (from 35% in 2025) as always-on AI becomes ubiquitous (wearables, hearables, smart home, industrial sensors). Data center/large computing power (PIM) will capture 45% (from 65% in 2025) but absolute revenue grows 100x. Key risks include: (1) NVIDIA/AMD integrating PIM-like capabilities into mainstream GPUs (e.g., NVIDIA Grace Hopper superchip architecture already reduces memory bottleneck — could delay stand-alone PIM adoption), (2) analog CIM precision/reliability failing to meet automotive grade (AEC-Q100), (3) software ecosystem fragmentation delaying enterprise adoption (customers stick with CUDA), (4) US-China trade restrictions (export controls on advanced DRAM/HBM could limit PIM adoption in China; China domestic PIM/CIM may diverge from global standards, fragmenting market).
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